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Viterbi Decoder (No External RAM, Soft Decision/SOVA Supported)

This is high-speed soft decision viterbi decoder core, which is widely used as the decoder of convolutional code. The architecture without using external RAM is adopted. Working with our depuncture IP, various code rate is available (2/3, 3/4, 4/5, 5/6,6/7, 7/8 etc).

Introduction

Product NoCode RateSoft-Output
Si25301/2No
Si2530-R31/3No
Si2530-S1/2Yes
Si2530-R3S1/3Yes

Four kinds of products are selectable to meet different demands.

Features

  • - Simplified ACS loop for high-speed design
  • - Convolutional code generator polynomial configurable
  • - Convolutional code constraint length (K) : >= 3
  • - Soft input data bit width (m) configurable
  • - Available hard input viterbi decoder (m=1)
  • - Support punctured convolutional codes
  • - Traceback length (t) configurable
  • - Support trellis initialization
  • - Support various trellis termination method (trellis termination, tail biting etc.)
  • - Path metric bit width configurable
  • - Support soft-output
  • - Available two type : high-speed, low-latency
  • - Latency
    high-speed type : t+(K-1)+ceil(t/(K-1))+4
    low-latency type : t+(K-1)+4
  • - Available unsuccessive input data by enable control
  • - Fully synchronous design using a single clock
  • - ASIC friendly design
  • - Support various code rate by using depuncture IP (Si2552)

Gate Count / Performance

  • - TSMC 90nm
    (Constraints : Clock Skew 20%, Using wire load model)

    Convolutional Code : (171,133)oct, K=7, m=5, t=48
    50Mbps : low-latency type
    100Mbps- : high-speed type
    Gate Count : based on 2-NAND
  • - Xilinx Virtex-5 (XC5VLX30-3)
    Convolutional Code : (171,133)oct, K=7, m=3, t=48

    high-speed typeSlice:1571Block RAM:0200Mbps(200MHz)
    low-latency typeSlice:937Block RAM:030Mbps(30MHz)
    Slice:1226Block RAM:010Mbps(10MHz)
Viterbi Decoder Image

Interface

Input
NameDescription
ICLKClock
IXRSTAsynchronous reset
IDATAG2[m-1:0]Input data 2 (*1)
IDATAG1[m-1:0]Input data 1
IDATAG0[m-1:0]Input data 0
IFORMATInput data format
IPUNCG2Puncture position 2 (*1)
IPUNCG1Puncture position 1
IPUNCG0Puncture position 0
ITBLEN[1:0]Traceback length
ITLS[K-2:0]Trellis initialization state
ITLSINI[1:0]Trellis initialization setting
ITAILS[K-2:0]Trellis termination state
ITAILINI[1:0]Trellis termination setting
IDATAENBDecode enable
ISTARTDecode start (trellis initialization)
IENDDecode end (trellis termination)
  • *1: Only for Si2530-R3, Si2530-R3S
  • *2: Only for Si2530-S, Si2530-R3S
Output
NameDescription
ODATADecoded data
OSDATA[s-1:0]Soft-output (*2)
OVALIDDecoded data enable
OFIRSTFirst decoded data
OLASTLast decoded data

Applications

  • - Communications (support various standards with convolutional code)

Customization

  • - Change code rate (1/4, 1/5 etc.)
  • - Dynamically variable generator polynomian

For more information/customization on Viterbi decoder, please contact us.

The content might change without a previous notice due to the improvement.